1. Technical Field
Disclosed is a synchronous semiconductor memory device. In particular, a circuit and a method for writing data into a synchronous semiconductor memory.
2. Discussion of the Related Art
The operational speed and performance of a synchronous dynamic random access memory SDRAM is improved over a dynamic random access memory (DRAM) when the SDRAM is operated in synchronization with an external system clock and there are frequent sequential data read/write operations.
The operational speed and performance of an SDRAM is further improved when both the rising and falling edges of the system clock is used in reading and writing data, i.e., the clock rate is effectively doubled. This memory device is called the double data rate (DDR) SDRAM. In a DDR SDRAM, a strobe signal, commonly referred to as “DQS”, is used in conjunction with the system clock to strobe and clock memory data.
U.S. Pat. No. 6,078,546 to Lee discloses a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. FIG. 1A shows an input circuit disclosed in the '546 patent which stores a pair of data which is synchronized with either the system clock signal or the data strobe signal. Referring to FIG. 1A, an externally applied data strobe signal DS is received during a data write operation. An edge detector 300 detects an edge of the data strobe signal DS and generates first and second internal strobe signals DS1 and DS2 in synchronization with rising and falling edges of the data strobe signal DS, respectively. The signals DS1 and DS2 are used to strobe the odd and even data into data registers 303A and 303B, respectively. A second edge detector 301 detects an active edge of a system clock. A delay circuit 304 delays the output of the second edge detector 301 and the delayed clock signal CLKD is used to output the data from the data registers to write driver 305.
FIG. 1B shows the structure of the data register 303. Referring to FIG. 1B, the first or the odd data of the pair of data is input first to unit cell R1, where it is strobed by strobe signal DS1 and the complement of DS1. The output of R1 is fed to R2. Unit cell R3 receives the even or the second data bit of the data pair. Unit cells R2 and R3 are both first strobed by a strobe signal DS2 (AWR) and its complement. DS2 (AWR) is a product of the DS2 strobe signal and the write pulse to synchronize the strobe signals to the write operation. The odd and even data pair is then output with clocking by the delayed clock signal CLKD.
FIG. 2 shows a timing diagram of the data write operations of the circuit of FIG. 1A. The timing diagram shows the strobe and clock operations for a 4-bit data string input from DIND. The storage cell RI stores the odd numbered data D0 and D2 of the data string in synchronism with internal data strobe signals DS1 and its complement/DS1. The storage cell R3 stores the even numbered D1 and D3 in synchronism with strobe signals DS2 and its complement/DS2. The write drivers are activated with the first active external clock signal CLK after the write command WR. Case I illustrates that the data reaches the register circuit 303 with the valid data strobe signals inputted after reference clock signal CLK(0), namely in a case where the value of the t DQSS is maximum. Case II illustrates that data reaches the register circuit 303 with the valid data strobe signals inputted before the reference clock signal CLK(0), namely, in the case where the value of the t DQSS is minimum. The disclosure of U.S. Pat. No. 6,078,546 in its entirety is incorporated by reference herein.
As operational speed of memory devices are further increased, the timing margin between the external system clock and the data strobe signal DS becomes shorter. Accordingly, a need exists for an improved system and method for writing a string of data into a synchronous memory device with increased timing margin.